board: k2g: Enable ECC byte lane

Enable ECC byte lane for k2g-evm

Signed-off-by: Lokesh Vutla <[email protected]>
Reviewed-by: Tom Rini <[email protected]>

diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 34606f4b2f77380dedbd58a874f2f14b497c8d82..6b92530e42101b6d0efa17ca02a3cf974155e28c 100644 (file)
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -65,9 +65,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
        while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
                ;
 
-       /* Disable ECC for K2G */
        if (cpu_is_k2g()) {
-               clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
+               setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
                clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
                clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
                clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);